CN 4.1
Intr-un microprocesor cu arhitectura load/store
Toti operanzii trebuie sa se gaseasca in registrii procesor
Toti operanzii trebuie sa se gaseasca in memorie
Operanzii se pot gasi in memorie cat si in registrii procesor
Intr-un microprocesor cu ahitectura register/memory
Operanzii se pot gasi atat in memorie cat si in registrii procesor
Toti operanzii trebuie sa se gaseasca in registri procesor
Toti operanzii trebuie sa se gaseasca in memorie
Pipeline-ul unui procesor MIPS contine urmatoarele etaje
IF,ID,EX,MA
IF,ID,OF,EX,MA
IF,OF,EX,MA
Procesorul MIPS este de tipul
Load/store
Register/memory
Load/memory
Cum este tratat hazardul de control la un microprocesor MIPS
La decodificarea unei microinstructiuni de salt blocul IF este blocat
La decodificarea unei microinstructiuni de salt blocul ID este blocat
La decodificarea unei microinstructiuni de salt blocul MA este blocat
Deblocarea blocului IF , in urma unui hazard de control , are loc
Dupa executia instructiunii de salt conditionat
Dupa decodificarea instructiunii de salt conditionat
Dupa executarea instructiunii care urmeaza dupa instructiunea de salt conditionat
Blocul Clock a unui microprocesor MIPS elaboreaza un semnal de frecventa
Variabila
Constanta
Fixa
Unitatile de microprocesor raspund cu un semnal done
Au terminat actiunea
Au inceput actiunea
Sunt pregatite sa inceapa o actiune
Un nou ciclu de ceas incepe atunci cand
Toate unitatile au raspuns cu un semnal done
Unitatea cea mai rapida a raspuns cu un semnal done
Unitatea cea mai lenta a inceput actiunea
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