F-22 Modules

What is a DDPE (Dual Data Processing Element)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

A generic signal processor that executes mathematically intensive functions like the state matrix multiplications and Fast Fourier Transform used in radar sginal processing to support radar, EW, and MS/W functions

What is a DSPE (Dual Signal Processing Element)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a DPE/1553 ( Data Processing Element/Mil-Std-1553)

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a DSPD (Dual Signal Prcessing Element/Data Processing Element)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a GBM (Global Bulk Memory)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a GWY (Gateway)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a LLSP (Low Latency Signal Processor)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a GPVI (Graphics Processor/Video Interface)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a UCIF (User Console Interface)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

What is a FNIU (Fiber Optic Transmit/Receive Network Interface)?

A dual function LRM containing both a DSPE and a DPE. Each element operates independently of the other and can be treated as individual entities.

The backbone of the CIP's digital processing capability that operates as a general purpose computer executing Ada code to support radar, EW, CNI, and MS/W functions.

Provides a bi-direction communication path between PI Bus segments within a CIP and between two CIPS via HSDB.

Uses a C-31 processor to provide the interface between the CNI front end and the CIP backplane via fiber optic line.

Provides low latency, high bandwidth communications between a CIP processing cluster and the sensors.

Features a DPE on the front side and 1553 on the backside.

Features a fiber optic interface to the cockpit Multi-Function Display.

Designed to provide bulk storage data for any and all functional elements that are in the CIP and primarily used for storage of large data files that are shared between processing elements.

A two-sided LRM featuring a DPE on the fron and a UCIF hardware on the backside.

F-22 Modules

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